Abstract:
A circuit-switched shared-memory multiprocessor based on the 2D spanning bus hypercube is described. This design eliminates most of the processing overhead attributed to message passing systems. Circuit switching allows the sender to transfer directly into the receiver's address space by establishing a dedicated transmission path between the two nodes. Thus, data sets for cascaded calculations (using separate processors) can be prepared directly in the following processor's address space. A system was designed as an extension to a VME-based multiprocessor. This work investigates the potential efficiency of a circuit-switched topology using a simulation model. A simulation model for the implementation was developed using the NETWORK II.5 simulation system. The simulation results are used to specify the performance requirements of a switching element for a hypercube-connected multiprocessor. Next, the design and the operation of the interconnection mechanism are detailed. The design was implemented and tested in 3 μm CMOS technology using the suite of Mentor Graphics tools to establish the connection and communication delay parameters for the system architecture. Using the derived VLSI switch parameters, the performance of the 2D spanning bus hypercube is compared against that of two message-passing architectures based on the binary hypercube and the spanning bus hypercube. In both cases, the circuit-switched shared-memory design significantly reduced the processing overhead and the delay times involved in data transfers
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