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Daniel J Sorin, Associate Professor

  


Daniel J Sorin

Dr. Daniel Sorin is an associate professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.

Contact Info:
Office Location:  209C Hudson Hall
Office Phone:  (919) 660-5439
Email Address:   send me a message
Web Page: http://www.ee.duke.edu/~sorin

Education:

PhD, University of Wisconsin - Madison, 2002
MS, University of Wisconsin - Madison, 1998
BS, Duke University, 1996
Research Interests: computer architecture

The primary focus of my research is computer architecture. This research includes work to: improve the dependability of computer architectures, design microarchitectures such that their designs are easier to validate, and develop memory system designs for multicore processors.

Specialties:

Computer Engineering
Computer Architecture
Fault Tolerance
Reliability
Awards, Honors, and Distinctions

Eta Kappa Nu
Intel Graduate Fellowship
NSF Early CAREER Award, National Science Foundation, 2005
Outstanding Graduate Research Award, University of Wisconsin
Phi Beta Kappa
Tau Beta Pi
Top of 2004 - Nanocomputing Research, Technology Research News
Teaching (Spring 2012):  (typical courses)

  • ECE 152.01, COMPUTER ARCHITECTURE Synopsis
    Hudson 125, MWF 10:20 AM-11:10 AM
  • ECE 152.02, COMPUTER ARCHITECTURE Synopsis
    TBA, F 07:30 PM-08:45 PM
Representative Publications   (More Publications)

  1. Meixner, A. and Sorin, D.J., Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures, 2006 International Conference on Dependable Systems and Networks (2006), pp. 10 pp. -  [abs].
  2. Bower, F.A. and Sorin, D.J. and Ozev, S., A mechanism for online diagnosis of hard faults in microprocessors, Proceedings. 38th Annual IEEE/ACM International Symposium on Microarchitecture (2006), pp. 12 pp. -  [abs].
  3. Meixner, A. and Sorin, D.J., Dynamic verification of sequential consistency, Proceedings. 32nd International Symposium on Computer Architecture (2005), pp. 482 - 93  [abs].
  4. Dwyer, C. and Lebeck, A.R. and Sorin, D.J., Self-assembled architectures and the temporal aspects of computing, Computer (USA), vol. 38 no. 1 (2005), pp. 56 - 64 [34]  [abs].
  5. Li, T. and Lebeck, A.R. and Sorin, D.J., Spin detection hardware for improved management of multithreaded systems, IEEE Trans. Parallel Distrib. Syst. (USA), vol. 17 no. 6 (2006), pp. 508 - 21 [78]  [abs].
  6. Carter, J.R. and Ozev, S. and Sorin, D.J., Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown, Proceedings. Design, Automation and Test in Europe, vol. Vol. 1 (2005), pp. 300 - 5  [abs].
  7. Bower, F.A. and Shealy, P.G. and Ozev, S. and Sorin, D.J., Tolerating hard faults in microprocessor array structures, 2004 International Conference on Dependable Systems and Networks (2004), pp. 51 - 60  [abs].
  8. Sorin, D.J. and Martin, M.M.K. and Hill, M.D. and Wood, D.A., SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, Proceedings 29th Annual International Symposium on Computer Architecture (2002), pp. 123 - 34 [ISCA.2002.1003568]  [abs].
Duties:

Daniel Sorin is an associate professor of Electrical and Computer Engineering and Computer Science. He received his Ph.D. from the University of Wisconsin in 2002. His reseach interests are in computer architecture.
Current Ph.D. Students