- Brown, April S. and Chou, Chia S. and Delaney, Michael J. and Hooper, Catherine E. and Jensen, Joseph F. and Larson, Lawrence E. and Mishra, Umesh K. and Nguyen, Loi D. and Thompson, Mark S., Low-temperature buffer AlInAs/GaInAs on InP HEMT technology for ultra-high-speed integrated circuits,
Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
pp. 143 - 146 .
(last updated on 2007/04/14)
A report is presented on the development of a planar low-temperature buffer AlInAs/GaInAs on InP high-electron-mobility transistor (HEMT) technology for use in digital and analog integrated circuits. This technology is attractive for circuit applications because of the high achievable fT and fmax, low output conductance and gate leakage current, and reduced susceptibility to backgating effects. Two alternative logic families--UFL and SCFL (source-coupled FET logic)--were chosen for the realization of digital circuits. Measurements on the UFL ring oscillators exhibited a minimum gate delay of 13 pS with a power dissipation of 1.1 mW/gate at room temperature. The gate delay rose to 25 pS when the power dissipation increased to 3 mW/gate. This gate delay is expected to drop significantly with reductions in diode level-shift series resistance and improvements in transistor fT. The most complex SCFL circuit tested was a divide-by-eight counter. The SCFL circuits were configured as flip-flops in the divide-by-eight mode. The circuit operated at a maximum clock rate of 12.5 GHz.
Logic Devices--Gates;Electronic Circuits, Flip Flop;Crystals--Epitaxial Growth;