Papers Published

1. Wang, S; Wang, R; Chakrabarty, K; Tahoori, MB, Multicast testing of interposer-based 2.5D ICs: Test-architecture design and test scheduling, Acm Transactions on Design Automation of Electronic Systems, vol. 23 no. 3 (February, 2018), pp. 1-25, Association for Computing Machinery (ACM) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on throughsilicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a major challenge to test 2.5D ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this article, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. By considering the trade-off between test-application time, test-power budget, and test quality, the proposed technique provides test schedules with minimum test-application time under constraints on power consumption and fault coverage. Compared to previous work, the proposed technique can reduce test-application time by up to 53.4% for benchmark designs while achieving higher fault coverage. Since the loss in fault coverage due to multicast testing is extremely small, we can use top-off patterns to achieve full fault coverage for the dies at negligible additional cost.