- Shen, M. and Jopling, J. and Massoud, H.Z., On the effects of carrier tunneling on the capacitance-voltage characteristics of ultrathin-oxide MOSFETs,
Meeting Abstracts, vol. MA 2005-02
pp. 1474 - .
(last updated on 2007/04/15)
In this paper, the effects of gate tunneling on the capacitance-voltage characteristics of deep-submicron MOS devices with ultrathin gate dielectrics are discussed. The extraction of device parameters of MOS-FETs with sub-2nm gate oxides, and predicting the dependence of the C(V) characteristics on device and operation parameters will be presented. A general-purpose distributed MOSFET model valid in all bias ranges is introduced that takes into account the effects of gate tunneling, device geometry, and parasitics. The carrier concentration, electrostatic potential, and tunneling current density distributions along the MOSFET channel depend on the channel length, the gate overlap dimensions, the oxide thickness, the dopant concentrations in all regions of the device, and the applied bias voltages. The source to channel and drain to channel transition regions play an important role in ultrashort channel lengths. The lateral transport of carriers along the channel and their tunneling in the gate dielectric result in potential and carrier concentration distributions that depend on the channel length. The oxide thickness plays the important role of determining the rate of carrier tunneling in the oxide. The use of long-channel MOSFETs in the electrical characterization of devices leads to specific considerations in the extraction of device parameters from experimental measurements. In order to account for these considerations, the effects of different MOS device parameters on their C(V) characteristics in the presence of gate tunneling are simulated using a distributed device model. The dependence of MOSFET C(V) characteristics on device parameters, gate geometry, and parasitics is especially emphasized. The methodology in extracting the values of the elements in the distributed model will be presented. The potential, carrier, and oxide tunneling current distributions in long-channel devices are substantially different from those in short-channel devices. In this work, a distributed small-signal MOSFET model was introduced to simulate its C(V) characteristics while accounting for gate tunneling and parasitic effects. Comparison of the simulation results with experiments, the limitations of deep-submicron MOSFET C(V) characterization, and new guidelines for MOS C(V)-based parameter extraction will be presented at the conference.
Capacitance;Electric potential;MOSFET devices;Parameter estimation;Mathematical models;