Publications [#66413] of Nan M. Jokerst

Papers Published

1. Cha, Cheolung and Huang, Zhaoran and Jokerst, Nan M. and Brooke, Martin A., Test-structure free modeling method for de-embedding the effects of pads on device modeling, Proceedings - Electronic Components and Technology Conference (2003), pp. 1694 - 1700, New Orleans LA, United States
   (last updated on 2007/04/16)

   Abstract:
   On-wafer measurements of devices always include the parasitic effects of probe pads, interconnections, and substrate resistance. In order to extract actual Device Under Test (DUT) parameters from the measurements, several on-wafer test structures such as open, short, and thru are normally required. Various calibration and de-embedding procedures have been developed to use these test structures. [2-11] In this paper a test structure free de-embedding method is demonstrated that finds and removes the influence of parasitics of pad and interconnections with a single measurement. The method uses structural building blocks to construct equivalent circuits of pads, interconnect, and the DUT itself. The equivalent circuit model parameters are extracted simultaneously from the measured s-parameters using the optimization routines in widely used simulators (HSPICE and ADS). The proposed correction procedure is verified by comparison with other methods using an Interdigitated Capacitor (IDC).

   Keywords:
   Semiconductor device testing;Semiconductor device models;Embedded systems;Electric resistance;Calibration;Equivalent circuits;Computer simulation;Optimization;