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Papers Published
- Firouzi, F; Ye, F; Vijayan, A; Koneru, A; Chakrabarty, K; Tahoori, MB, Re-using BIST for circuit aging monitoring,
Proceedings 2015 20th Ieee European Test Symposium, Ets 2014
(June, 2015), IEEE [doi] .
(last updated on 2022/12/30)Abstract:
Bias Temperature Instability (BTI)-induced transistor aging degrades path delay over time and may eventually induce circuit failure due to timing violations. Chip health monitoring is therefore necessary to track delay changes on a per-chip basis. We propose a method to accurately predict the fine-grained circuit-delay degradation with minimal area and performance overhead. It re-uses on-chip design-for-test (DfT) infrastructure to track the severity of run-time stress by periodiclly capturing system state and compacting it using a multiple input signature register (MISR). The captured stress information is fed to a software-based prediction model in realtime. The prediction model is trained offline using support vector regression. Aging prediction based on run-time stress monitoring can be used to proactively activate aging mitigation techniques. Experimental results for benchmark circuits highlight the accuracy of the proposed approach.