Papers Published

1. Lien, WC; Lee, KJ; Chakrabarty, K; Hsieh, TY, Output selection for test response compaction based on multiple counters, Technical Papers of 2014 International Symposium on Vlsi Design, Automation and Test, Vlsi Dat 2014 (January, 2014), IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.1 © 2014 IEEE.