Papers Published

1. Vartziotis, F; Kavousianos, X; Chakrabarty, K; Parekhji, R; Jain, A, Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing, Proceedings Design, Automation and Test in Europe, Date (January, 2014) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly increasing the effectiveness of multi-site testing. However, TDM suffers from some inherent limitations that do not allow the fullest possible exploitation of TAM bandwidth. To overcome these limitations, we propose space-division multiplexing (SDM), which complements TDM and offers higher multi-site test efficiency. We implement space-and time-division multiplexing (STDM) using a new, scalable test-time minimization method based on a combination of bin packing and simulated annealing. Results for industrial SoCs, highlight the advantages of the proposed optimization method. © 2014 EDAA.