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Papers Published
- Xiang, D; Liu, G; Chakrabarty, K; Fujiwara, H, Thermal-Aware test scheduling for NOC-based 3D integrated circuits,
Ieee/Ifip International Conference on Vlsi and System on Chip, Vlsi Soc
(January, 2013),
pp. 96-101, IEEE [doi] .
(last updated on 2022/12/30)Abstract:
A 3D stacked network-on-chip (NOC) promises the integration of a large number of cores in a many-core system-on-chip (SOC). The NOC can be used to test the embedded cores in such SOCs, whereby the added cost of dedicated test-Access hardware can be avoided. However, a potential problem associated with a 3D NOC-based test access is the emergence of hotspots due to stacking and the high toggle rates associated with structural test patterns used for manufacturing test. High temperatures and hotspots can lead to the failure of good parts, resulting in yield loss. We describe a thermal-driven test scheduling method to avoid hotspots, whereby the full NOC bandwidth is used to deliver test packets. Test delivery is carried out using a new unicast-based multicast scheme. Experimental results highlight the effectiveness of the proposed method in reducing test time under thermal constraints. © 2013 IEEE.