Papers Published

1. Noia, B; Chakrabarty, K, Retiming for delay recovery after DfT insertion on interdie paths in 3-D ICs, Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 33 no. 3 (March, 2014), pp. 464-475, Institute of Electrical and Electronics Engineers (IEEE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3-D integrated circuits. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for KGD test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond through-silicon-via (TSV) and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to TSV paths by design-for-test insertion. Retiming is performed at both die and stack level, and a logic redistribution is proposed to improve the results of die-level retiming. The proposed methods are evaluated through simulations using two logic-on-logic 3-D benchmarks and one modular processor partitioned between two dies. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells in cores where all logic and dies are unfixed. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming. © 2013 IEEE.