Papers Published

1. Deutsch, S; Chakrabarty, K, Robust optimization of test-architecture designs for core-based SoCs, Proceedings 2013 18th Ieee European Test Symposium, Ets 2013 (September, 2013), IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Today's technology allows for the integration of man: cores in a single die, for instance, in core-based SoCs, and an even larger number of cores are likely to be integrated over multiple layer in a 3D stack. In order to minimize test cost, the test architecture in: core-based SOC is optimized for minimum test time. Optimization methods in use today assume that all relevant input parameters such as core test time and power consumption during test, ar known at the design stage. However, these parameters can chang after manufacturing and, in that scenario, the originally designe test architecture may no longer be optimal. Moreover, conventiona optimization methods have to consider worst-case estimates fo all input parameters to ensure feasibility, which can result in conservative and hence expensive solutions. We propose the use of robust optimization for test-architecture design and test scheduling This goal of this approach is to find a solution that remains clos to optimal in the presence of parameter variations. Experimental results for the ITC'02 SoC benchmarks show that, compared to optimization methods that target only a single point in the input parameter space, robust optimization can better optimize test tim in the presence of parameter variations © 2013 IEEE.