Papers Published

1. Liu, C; Chakrabarty, K; Jone, WB, System/Network-On-Chip Test Architectures (December, 2008), pp. 171-224, Elsevier [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Rapid advances in test development techniques are needed to reduce the test cost of million-gate system on chip (SOC) devices. This chapter presents techniques that facilitate low-cost modular testing of SOCs. Topics discussed here include techniques for wrapper design, test access mechanism optimization, test scheduling, and applications to mixed-signal and hierarchical SOCs. Recent work on the testing of embedded cores with multiple clock domains and wafer sort of core-based SOCs are also discussed. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test cost. The discussion is then extended to the testing of NOC-based designs, including reuse of on-chip network for core testing, test scheduling, test access methods and interface, efficient reuse of the network, power-aware and thermal-aware testing, and on-chip network including interconnects, routers, and network interface testing. Finally, two case studies, one for SOC testing and the other for NOC testing, are presented based on industrial chips developed by Philips. Future research and development are needed to provide an integrated platform and a set of methodologies that are suitable for various networks such that the design and test cost of the overall NOC-based system (both cores and network) can be reduced. © 2008 Elsevier Inc. All rights reserved.