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Papers Published
- Agrawal, M; Chakrabarty, K, Test-cost optimization and test-flow selection for 3D-stacked ICs,
Proceedings of the Ieee Vlsi Test Symposium
(August, 2013), IEEE [doi] .
(last updated on 2022/12/30)Abstract:
Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic solution, which is compared to an exact approach for a small test case and to a random-selection baseline method for large test cases. © 2013 IEEE.