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Papers Published
- Sehgal, A; Dubey, A; Marinissen, EJ; Wouters, C; Vranken, H; Chakrabarty, K, Yield analysis for repairable embedded memories,
Proceedings of the European Test Workshop, vol. 2003-January
(January, 2003),
pp. 35-40, IEEE Comput. Soc [Gateway.cgi], [doi] .
(last updated on 2022/12/30)Abstract:
Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.