Papers Published

1. Chandra, A; Chakrabarty, K, Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding, edited by Nebel, W; Jerraya, A, Proceedings Design, Automation and Test in Europe, Date (December, 2001), pp. 145-149, IEEE Comput. Soc [mostRecentIssue.jsp], [doi] .
   (last updated on 2022/12/30)

   Abstract:
   We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the internal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits. © 2001 IEEE.