Papers Published

1. Chandra, A; Chakrabarty, K, Test resource partitioning for SOCs, Ieee Design & Test of Computers, vol. 18 no. 5 (September, 2001), pp. 80-91, Institute of Electrical and Electronics Engineers (IEEE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Test resource partitioning (TRP), a new approach for testing system on a chip (SOC) is presented. In order to overcome the limitations of conventional automatic test equipment (ATE) techniques, TRP is introduced. TRP approach is based on test data compression and on-chip decompression. Further TRP reduces the test data volume and testing time and also uses slower testers without decreasing test quality.