Papers Published

1. Tehranipoor, M; Nourani, M; Chakrabarty, K, Nine-coded compression technique for testing embedded cores in SoCs, Ieee Transactions on Very Large Scale Integration (Vlsi) Systems, vol. 13 no. 6 (June, 2005), pp. 719-730, Institute of Electrical and Electronics Engineers (IEEE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at pre-computed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the pre-computed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique. © 2005 IEEE.