Papers Published

1. Kavousianos, X; Chakrabarty, K; Jain, A; Parekhji, R, Test scheduling for multicore SoCs with dynamic voltage scaling and multiple voltage islands, Proceedings of the Asian Test Symposium (December, 2011), pp. 33-39, IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast heuristic test scheduling technique for multicore chips that minimize the testing time when each core is tested at multiple voltage settings as well as if it is tested for state retention when the core switches between two voltage levels. Experimental results for two test-case SOCs from industry highlight the effectiveness of the proposed method. © 2011 IEEE.