Papers Published

1. Jiang, L; Xu, Q; Chakrabarty, K; Mak, TM, Integrated test-architecture optimization and thermal-aware test scheduling for 3-D SoCs under pre-bond test-pin-count constraint, Ieee Transactions on Very Large Scale Integration (Vlsi) Systems, vol. 20 no. 9 (January, 2012), pp. 1621-1633 [doi] .
   (last updated on 2022/12/30)

   Abstract:
   We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated with three-dimensional (3-D) integration technology. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for test-access mechanisms. In addition, a thermal-aware test scheduling algorithm is proposed to eliminate hot spots during manufacturing test. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution. © 2012 IEEE.