Papers Published

1. Hsu, CY; Kuo, CY; Li, JCM; Chakrabarty, K, 3D IC test scheduling using simulated annealing, 2012 International Symposium on Vlsi Design, Automation and Test, Vlsi Dat 2012 Proceedings of Technical Papers (July, 2012) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge. High power density in 3D ICs causes rising temperature, which may cause test yield loss. In this paper, we propose a thermal-aware test scheduling technique for 3D ICs. Our experimental results show that the maximum temperature in the test schedule of our proposed technique is under the temperature limit while the test length overhead is only 19%. © 2012 IEEE.