Papers Published

1. Chakrabarty, K; Hayes, JP, DFBT: a design-for-testability method based on balance testing, Proceedings Design Automation Conference (December, 1994), pp. 351-357 .
   (last updated on 2022/12/30)

   Abstract:
   We present design for balance testability (DFBT), a systematic signature-based method for enhancing the testability of logic circuits. DFBT employs balance testing and guarantees 100% coverage of single stuckline faults, as well as many multiple stuck-line and bridging faults. The logic overhead of DFBT is modest - only one extra I/O pin and a small number of extra gates - and the original circuit need not be altered. We illustrate DFBT by applying it to representative logic circuits.