Papers Published

1. Sehgal, A; Iyengar, V; Krasniewski, MD; Chakrabarty, K, Test cost reduction for SOCs using virtual TAMs and lagrange multipliers, Proceedings Design Automation Conference (January, 2003), pp. 738-743 [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high-speed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks.