Papers Published

1. Chakrabarty, K, A synthesis-for-transparency approach for hierarchical and system-on-a-chip test, Ieee Transactions on Very Large Scale Integration (Vlsi) Systems, vol. 11 no. 2 (April, 2003), pp. 167-179, Institute of Electrical and Electronics Engineers (IEEE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Test data propagation through modules and test vector translation are two major challenges encountered in hierarchical testing. We propose a new synthesis-for-test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system. This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores. The embedded multiplexers provide complete single-cycle transparency, thereby offering a straightforward yet effective solution to the problems of test data propagation and test vector translation. In order to determine module I/O bitwidths for single-cycle transparency, a global analysis is carried out using a graph-theoretic framework and an optimization method based on integer linear programming. Case studies using high-level synthesis benchmarks and an industrial-strength benchmark show that synthesis for transparency introduces very little area and performance overhead.