Papers Published

1. Yu, TE; Yoneda, T; Chakrabarty, K; Fujiwara, H, Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints, Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac (April, 2009), pp. 793-798, IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning, test inter-leaving, and bandwidth matching. We use a computationally tractable thermal-cost model to ensure that temperature constraints are satisfied and the test application time is minimized. Simulation results for the ITC'02 SOC Test Benchmarks show that, compared to prior thermal-aware test-scheduling techniques, the proposed method leads to shorter test times under tight temperature constraints. © 2009 IEEE.