Papers Published

1. Fang, H; Chakrabarty, K; Parekhji, R, Bit-operation-based seed augmentation for LFSR reseeding with high defect coveraged, Proceedings of the Asian Test Symposium (December, 2009), pp. 331-336, IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   We present a design-for-testability (DFT) technique for increasing the effectivenessof LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseedingusing output deviations alone, the proposed method provides higher coverage for transitiondelay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtainedwith the proposed LFSR reseeding method using a smaller number of seeds. © 2009 IEEE.