Papers Published

1. Yu, TE; Yoneda, T; Chakrabarty, K; Fujiwara, H, Thermal-aware test access mechanism and wrapper design optimization for system-on-chips, Ieice Transactions on Information and Systems, vol. E91-D no. 10 (January, 2008), pp. 2440-2448, Institute of Electronics, Information and Communications Engineers (IEICE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.