Papers Published

1. Wang, R; Chakrabarty, K, Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions, Proceedings of the Asian Test Symposium (December, 2016), pp. 74-79, IEEE [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias. This paper describes some of the major challenges related to testing of 2.5D ICs and presents some solutions to these problems. We first describe a test architecture using e-fuses for pre-bond interposer testing. We next present an efficient built-in self-test (BIST) technique that targets the dies and the interposer interconnects. Finally, we present a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.