Papers Published

1. Wang, R; Chakrabarty, K, Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits, Ieee Design & Test, vol. 34 no. 5 (October, 2017), pp. 72-79, Institute of Electrical and Electronics Engineers (IEEE) [doi] .
   (last updated on 2022/12/30)

   Abstract:
   Editor's note: 2.5-D integrated circuit (IC) is a cost-efficient alternative to through-silicon-via (TSV)-based 3-D IC. In this paper, the authors give a comprehensive summary of the testing challenges of 2.5-D ICs and their existing solutions. They then present a test architecture using e-fuses for prebond interposer testing and a method to reduce power-supply noise during the testing. - Yiran Chen, Duke University.