Papers Published

1. Vartziotis, F; Kavousianos, X; Georgiou, P; Chakrabarty, K, A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-$V-{\mathrm{ dd}}$ SoCs, Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 36 no. 11 (November, 2017), pp. 1911-1924 [doi] .
   (last updated on 2022/12/30)

   Abstract:
   The use of multiple voltage levels introduces new challenges for testing multi-Vdd systems-on-chip (SoCs). Timedivision-multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the test-accessmechanism (TAM) in the SoC. Single-Vdd TAM optimization techniques consider neither the highly constrained test environment of multi-Vdd SoCs nor the benefits provided by TDM, therefore they are not suitable for multi-Vdd SoCs. In this paper, we propose the first TAM optimization technique for multi-Vdd SoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a branch-&-bound approach, it quickly identifies the most effective TAM configurations. Experiments using large benchmark SoCs as well as SoCs from industry highlight the benefits of the proposed technique on multi-Vdd designs, for both single-site and multisite test applications.