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- Goel, SK; Chakrabarty, K, Preface
(January, 2017),
pp. x-xii, CRC Press [doi] .
(last updated on 2022/12/30)Abstract:
© 2014 by Taylor & Francis Group, LLC. Advances in design methods and process technology are continuing to push the envelope for integrated circuits. The use of advanced process technology brings forward several design and test challenges. In addition to manufacturing defects such as resistive opens/bridges, design-related issues such as process variation, power supply noise, cross talk, and design-for-manufacturability (DfM) rule violations such as butted contacts or insufficient via enclosures introduce small additional delays in the circuit [Mitra 2004; Kruseman 2004]. These delays are commonly referred to as small-delay defects (SDDs), and testing them is one of the major challenges that the semiconductor industry is facing today. SDDs can cause immediate failure of a circuit if introduced on critical paths, whereas they cause major quality concerns if they occur on noncritical paths. For very-high-quality products (0-100 defective parts per million [DPPM]), testing SDDs is necessary.