Papers Published

1. Robinson, William H. and Wills, D. Scott and Brooke, Martin and Jokerst, Nan, IRIS: An integrated, scalable focal plane architecture, Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS, vol. 2 (1998), pp. 184 - 185 [LEOS.1998.739522] .
   (last updated on 2007/04/11)

   Abstract:
   Wearable video processing systems integrate low cost silicon detectors and analog interface circuitry with massively parallel digital processing on a single chip. While this `imaging system on a chip' can enable many significant new systems, many architectural and technological challenges must be addressed. This paper presents the IRIS architecture in which a detector, analog interface circuitry, and massively parallel digital processing is integrated into a cell that can be tiled into a monolithic array. This pixel level integration offers significant performance, efficiency, and cost advantages over multi-chip and non-interleaved approaches. The IRIS architecture and an example system is described.

   Keywords:
   Detectors;Integrated circuit layout;Digital signal processing;Cost effectiveness;