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Publications [#163043] of Krishnendu Chakrabarty

Papers Published

  1. S. Bahukudumbi and S. Ozev and K. Chakrabarty and V. Iyengar, Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs, Ieee Transactions On Very Large Scale Integration (vlsi) Systems, vol. 17 no. 4 (April, 2009), pp. 587 -- 592, ISSN 1063-8210
    (last updated on 2009/09/08)

    Abstract:
    Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of "big-D/small-A" mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal "big-D/small-A" SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.


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