Publications [#285476] of Nikos Pitsianis

Papers Published

1. Pitsianis, NP; Pechanek, GG, Indirect VLIW memory allocation for the ManArray multiprocessor DSP, Comput. Archit. News (USA), vol. 31 no. 1 (2003), pp. 69-74, Association for Computing Machinery (ACM) [773365.773373], [doi]
   (last updated on 2026/01/20)

   Abstract:
   The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManAffay family of multiprocessor digital signal processors (DSP) provides a scalable alternative to the wide instruction busses usually required in a multiprocessor VLIW DSP. The ManArray processors indirectly access VLIWs from small caches of VLIWs localized in each processing element. With this work, we present an algorithm to perform 1) iVLIW instruction memory allocation on multiple processing elements to minimize instruction memory requirements and 2) scheduling of the iVLIW setup instructions to minimize execution overhead. We present preliminary experimental results that demonstrate the effectiveness of our approach

   Keywords:
   cache storage;instruction sets;minimisation;multiprocessing systems;signal processing;