Publications [#67751] of Richard B. Fair

Papers Published

1. Fair, Richard B. and Wortman, Jimmie J. and Liu, Jiann and Tischler, Mike and Masnari, Nino A., MODELING PHYSICAL LIMITATIONS ON JUNCTION SCALING FOR CMOS., IEEE Transactions on Electron Devices, vol. ED-31 no. 9 (1984), pp. 1180 - 1185
   (last updated on 2007/04/17)

   Abstract:
   Accurate calculations of diffusion and ion-implantation processes in silicon require the utilization of complex steady-state physical models that include the effects of both vacancies and self-interstitials. A new one-dimensional computer program, PROSIM II, has been developed for use in experimental junction formation studies that impact on advanced MOS technologies. PROSIM II has been used to study the scaling limits of counter-doped junctions for CMOS using both conventional furnace annealing and rapid thermal annealing processes. It is found that double implants of boron and arsenic can be used to produce a minimum 3000-A-deep junction and still satisfy sheet resistance requirements for a 1- mu m process.

   Keywords:
   SEMICONDUCTOR DEVICES, MOS - Junctions;COMPUTER SIMULATION;HEAT TREATMENT - Annealing;BORON;ARSENIC;