Publications [#64763] of Hisham Z. Massoud

Papers Published

1. Wu, Y. and Lucovsky, G. and Massoud, H.Z., Improvement of gate dielectric reliability for p⁺ poly MOS devices using remote PECVD top nitride deposition on thin gate oxides, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173) (1998), pp. 70 - 5, Reno, NV, USA [RELPHY.1998.670446]
   (last updated on 2007/04/15)

   Abstract:
   Dual layer dielectrics have been formed by remote PECVD of ultra-thin (0.4~1.2 nm) nitrides on thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p⁺ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal for 1~4 minutes at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C-V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However, there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p⁺ poly-Si gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability

   Keywords:
   annealing;CMOS integrated circuits;dielectric thin films;diffusion;doping profiles;electronic density of states;elemental semiconductors;integrated circuit reliability;integrated circuit testing;interface states;MOS capacitors;MOSFET;nitridation;plasma CVD;silicon;